【公開日：2025.06.16】【最終更新日：2025.04.17】
課題データ / Project Data
課題番号 / Project Issue Number
22UT0412
利用課題名 / Title
Low Temperature Measurement of Silicon Double Quantum Dot Device
利用した実施機関 / Support Institute
東京大学 / Tokyo Univ.
機関外・機関内の利用 / External or Internal Use
内部利用（ARIM事業参画者以外）/Internal Use (by non ARIM members)
技術領域 / Technology Area
【横断技術領域 / Cross-Technology Area】（主 / Main）計測・分析/Advanced Characterization（副 / Sub）-
【重要技術領域 / Important Technology Area】（主 / Main）高度なデバイス機能の発現を可能とするマテリアル/Materials allowing high-level device functions to be performed（副 / Sub）-
キーワード / Keywords
環境制御マニュアルプローバステーション,量子効果デバイス/ Quantum effect device
利用者と利用形態 / User and Support Type
利用者名（課題申請者）/ User Name (Project Applicant)
KIM Junoh
所属名 / Affiliation
東京大学
共同利用者氏名 / Names of Collaborators in Other Institutes Than Hub and Spoke Institutes
ARIM実施機関支援担当者 / Names of Collaborators in The Hub and Spoke Institutes
利用形態 / Support Type
（主 / Main）機器利用/Equipment Utilization（副 / Sub）-
利用した主な設備 / Equipment Used in This Project
報告書データ / Report
概要（目的・用途・実施内容）/ Abstract (Aim, Use Applications and Contents)
Silicon double quantum dots device in which carriers are confined within two quantum dots, have attracted attention because they can be used for various research applications related to quantum physics and electronics, such as spin based silicon quantum bits, sensor transistors, and single-electron pumps[1-3]. In this study, we fabricated silicon double quantum dots with two fine gates adjacent to each other on the silicon nanowire, and confirmed its operation at low temperature.
実験 / Experimental
SEM images and schematic diagrams of the silicon double quantum dot structure fabricated in this study are shown in Fig. 1. Silicon nanowire with the width of 40 nm, thickness of 18 ~ 20 nm, length of 700 nm, and gate oxide thickness of 10 nm was fabricated by electron beam lithography (EBL), dry etching, and thermal oxidation on the SOI substrate. Next, fine gates (G1 and G2) were formed by EBL and dry etching of phosphorus-doped polysilicon. The width of each fine gate is 70 nm and the pitch between gates is 130 nm. Finally, the global Top Gate (TG) was formed by depositing an oxide film and polysilicon by LPCVD, and ion implantation was performed using the TG as a mas
結果と考察 / Results and Discussion
Current-voltage measurements of the device fabricated in this study was performed at T=16.5 K using a B1500A semiconductor device analyzer and a CRX-4K probe station. Fig. 2 shows the current-voltage characteristics when VG1 and VG2 were varied at drain voltage VD= 5 mV and TG voltage VTG =2.5 V . From the results of Fig. 2, it was found that the drain current oscillates with changes in the voltages of G1 and G2. This result is due to the coulomb blockade and confirms the formation of quantum dots in the fabricated device.
図・表・数式 / Figures, Tables and Equations
Fig. 1 (a) SEM image, (b) schematic 3D view, and (c) schematic cross section of the fabricated device
Drain current and VG1 characteristics at T = 16.5 K when VG2 is changed. Clear current oscillation due to coulomb blockade was observed.
その他・特記事項（参考文献・謝辞等） / Remarks(References and Acknowledgements)
[1] R. Maurand et al., Nat Comm., 7, 13575, 2016. [2] F. Ansaloni et al., Nat Comm., 11, 6399 2020. [3] T. Tanttu et al., New J. Phys. 17 103030, 2015.謝辞：本研究の一部はJSPS科研費 JP19H00754の助成を受けた．
成果発表・成果利用 / Publication and Patents
論文・プロシーディング（DOIのあるもの） / DOI (Publication and Proceedings)
口頭発表、ポスター発表および、その他の論文 / Oral Presentations etc.
- J. Kim, T. Mizutani, T. Saraya, H. Oka, T. Mori, M. Kobayashi, and T. Hiramoto, 第70回応用物理学会春季学術講演会, 2023年3月
特許 / Patents
特許出願件数 / Number of Patent Applications：0件
特許登録件数 / Number of Registered Patents：0件