【公開日：2025.06.10】【最終更新日：2025.05.01】
課題データ / Project Data
課題番号 / Project Issue Number
24NM5238
利用課題名 / Title
Carbon nanotube molecular junction devices
利用した実施機関 / Support Institute
物質・材料研究機構 / NIMS
機関外・機関内の利用 / External or Internal Use
内部利用（ARIM事業参画者以外）/Internal Use (by non ARIM members)
技術領域 / Technology Area
【横断技術領域 / Cross-Technology Area】（主 / Main）加工・デバイスプロセス/Nanofabrication（副 / Sub）物質・材料合成プロセス/Molecule & Material Synthesis
【重要技術領域 / Important Technology Area】（主 / Main）次世代ナノスケールマテリアル/Next-generation nanoscale materials（副 / Sub）高度なデバイス機能の発現を可能とするマテリアル/Materials allowing high-level device functions to be performed
キーワード / Keywords
蒸着・成膜/ Vapor deposition/film formation,ALD,スパッタリング/ Sputtering,光リソグラフィ/ Photolithgraphy,ダイシング/ Dicing,原子層薄膜/ Atomic layer thin film,ナノカーボン/ Nano carbon,ナノチューブ/ Nanotube,MEMS/NEMSデバイス/ MEMS/NEMS device
利用者と利用形態 / User and Support Type
利用者名（課題申請者）/ User Name (Project Applicant)
湯 代明
所属名 / Affiliation
物質・材料研究機構
共同利用者氏名 / Names of Collaborators in Other Institutes Than Hub and Spoke Institutes
PICHEAU Emmanuel Vincent David
ARIM実施機関支援担当者 / Names of Collaborators in The Hub and Spoke Institutes
IKEDA Naoki,FUJII Michiko,OHI Akihiko
利用形態 / Support Type
（主 / Main）機器利用/Equipment Utilization（副 / Sub）,技術補助/Technical Assistance
利用した主な設備 / Equipment Used in This Project
NM-604：マスクレス露光装置 [DL-1000/NC2P]
NM-665：電子銃型蒸着装置 [ADS-E810]
NM-616：シリコンDRIE装置 [ASE-SRE]
NM-614：CCP-RIE装置 [RIE-200NL]
NM-644：原子層堆積装置 [SUNALE R-150]
報告書データ / Report
概要（目的・用途・実施内容）/ Abstract (Aim, Use Applications and Contents)
Carbon nanotubes (CNT) have received great interest in various fields including high performance opto-electronic. Since their properties directly inherit from their chirality (i.e. structure), it has been proposed for decades to exploit a local change of chirality to fabricate new types of transistors. This concept has been demonstrated in our group by in-situ Transmission Electron Microscope (TEM) experiments a few years ago (Science 374,1616-1620 (2021)). The current project is an extension of this research. The aim is to use MEMS fabrication technics to create devices for in-situ TEM experiments. The devices should integrate functionalities (e.g. electrodes or heating ability), an open window on a suspended membrane for TEM observation of the CNT and preferably be compatible with CNT growth conditions (resistant to 975 °C). The goal is to have a platform to study further the local change of charity mechanism, to exploit it in devices for different purposes (transistors, resonators, etc.) and to demonstrate the large-scale applicability of the concept.
実験 / Experimental
The fabrication is made on a commercial silicon wafer (300 µm) both side polished and coated with 100 nm SiO2 and 100 nm Si3N4 layers (wafer pro). First, suspended membranes are created: following a photolithography step to define the area to be exposed (Maskless Lithography [DL-1000/NC2P]), the SiO2/Si3N4 layer is first etched by reactive ion etching using CHF3 gas (CCP-RIE [RIE-200NL]) on the back side of the wafer. The wafer is then immersed in a 40% KOH solution at various temperature/time to obtain suspended membranes of desirable thickness and made of Si/SiO2/Si3N4. Following, electrodes are created by lift off process (Maskless Lithography [DL-1000/NC2P], EB Evaporator [MB-501010], [ADS-E86], [ADS-E810]). Different metals/thickness are under exploration. So far, the best results (adhesion, definition, thermal resistance) have been obtained with Ti(5nm)/Au(150nm). Finally, slits are patterned on the suspended membranes (Maskless Lithography [DL-1000/NC2P]) and opened by successive reactive ion etching steps (CCP-RIE [RIE-200NL]) for Si3N4/SiO2 and Si Deep RIE [ASE-SRE] for silicon). The fabrication will soon include the deposition of a dielectric layer by atomic layer deposition (tentative: ALD [SUNALE R-150]) and later pattern by EB-Lithography for nanometric width slits.
結果と考察 / Results and Discussion
Different devices have been designed. We will report on two kinds of devices already made and the design of the next one to be tested. First, we have fabricated chips to be used as TEM grids for different TEM holders (accepting circular or rectangular chips). Those grids are a simple version of the devices to be used later because they do not include electrodes. Figure 1 shows the fabrication process of those grids. From left to right, we can see the KOH etching process after the back window opening, the 20 µm thick resulting membrane formed (slit patterning by photoresist on top), the wafer after silicon deep etching, and the resulting TEM grid. We can see on the second picture that a membrane appears red. It corresponds to the light transmitted by the membrane from a white light source and the color depends on the membrane thickness. We can see on the last picture, bottom, photoresist residue after its removal. This is a problem that we usually face with photoresist exposed to the silicon deep etching process and that we are trying to solve. So far, our best result has been obtained by thermal oxidation of the photoresist at 1000 °C.The second design presented aimed the fabrication of heating devices. The design is presented on figure 2 (top) and is made of a metallic coil deposited on top of a suspended membrane, isolated from the rest of the chip. A slit for TEM observation has been introduced between electrodes allowing a transistor configuration measurement. Figure 2 (bottom) shows the characterization of the device. This prototype allows heating up to ~130 °C with a bias of ~ 60 V, demonstrating the possibility to fabricate such devices at NIMS, and will be optimized.Finally, the next device currently under fabrication is for in-situ measurement of FET configuration of CNT inside TEM. Its design is shown in figure 3. For this device, electrodes are deposited. The area to be observed includes a gate electrode deposited on top of a suspended membrane. A slit will be open for observation and the gate electrode will be covered by a dielectric layer.
図・表・数式 / Figures, Tables and Equations
Figure 1: Fabrication of TEM grids for different TEM holders on silicon wafer.
Figure 2: Design (top) and characterization (bottom) of heating device.
Figure 3: Device to measure FET configuration of a CNT inside a TEM.
その他・特記事項（参考文献・謝辞等） / Remarks(References and Acknowledgements)
成果発表・成果利用 / Publication and Patents
論文・プロシーディング（DOIのあるもの） / DOI (Publication and Proceedings)
-
Hai-Bo Zhao, Diameter-dependent thermal conductivity of carbon nanotubes, Journal of Materials Science & Technology, 221, 46-53(2025).
DOI: 10.1016/j.jmst.2024.09.019
-
Monika R. Snowdon, Iptycene-Assisted Alignment of Chirality-Sorted SWCNTs for Field-Effect Transistors, ACS Applied Nano Materials, 8, 944-951(2025).
DOI: 10.1021/acsanm.4c04305
-
Lili Zhang, Growth Mechanism of Carbon Nanotubes Revealed by in situ Transmission Electron Microscopy, Small, 20, (2024).
DOI: 10.1002/smll.202405736
-
Guohai Chen, Machine Learning as a “Catalyst” for Advancements in Carbon Nanotube Research, Nanomaterials, 14, 1688(2024).
DOI: 10.3390/nano14211688
口頭発表、ポスター発表および、その他の論文 / Oral Presentations etc.
- D.M. Tang, Chirality engineering for carbon nanotube electronics by in situ TEM, the 13th Asia Pacific Microscopy Congress 2025, Brisbane, 2nd - 7th February 2025.
特許 / Patents
特許出願件数 / Number of Patent Applications：0件
特許登録件数 / Number of Registered Patents：0件